                Silicon Errata and Software Workarounds
                =======================================

It is an unfortunate fact of life that hardware is often produced with
so-called "errata", which can cause it to deviate from the architecture
under specific circumstances.  For hardware produced by ARM, these
errata are broadly classified into the following categories:

  Category A: A critical error without a viable workaround.
  Category B: A significant or critical error with an acceptable
              workaround.
  Category C: A minor error that is not expected to occur under normal
              operation.

For more information, consult one of the "Software Developers Errata
Notice" documents available on infocenter.arm.com (registration
required).

As far as Xen is concerned, Category B errata may require some special
treatment in the hypervisor. For example, avoiding a particular sequence
of code, or configuring the processor in a particular way. A less common
situation may require similar actions in order to declassify a Category A
erratum into a Category C erratum. These are collectively known as
"software workarounds" and are only required in the minority of cases
(e.g. those cases that both require a non-secure workaround *and* can
be triggered by Xen).

For software workarounds that may adversely impact systems unaffected by
the erratum in question, a Kconfig entry is added under "ARM errata
workarounds via the alternatives framework". These are enabled by default
and patched in at runtime when an affected CPU is detected. Note that
runtime patching is only supported on ARM64. For less-intrusive workarounds,
a Kconfig option is not available and the code is structured (preferably
with a comment) in such a way that the erratum will not be hit.

This approach can make it slightly onerous to determine exactly which
errata are worked around in an arbitrary hypervisor source tree, so this
file acts as a registry of software workarounds in the Xen hypervisor and
will be updated when new workarounds are committed and backported to
stable hypervisors.

| Implementor    | Component       | Erratum ID      | Kconfig                 |
+----------------+-----------------+-----------------+-------------------------+
| ARM            | Cortex-A15      | #766422         | N/A                     |
| ARM            | Cortex-A53      | #827319         | ARM64_ERRATUM_827319    |
| ARM            | Cortex-A53      | #824069         | ARM64_ERRATUM_824069    |
| ARM            | Cortex-A53      | #819472         | ARM64_ERRATUM_819472    |
| ARM            | Cortex-A53      | #843419         | ARM64_ERRATUM_843419    |
| ARM            | Cortex-A53      | #1530924        | N/A                     |
| ARM            | Cortex-A55      | #1530923        | N/A                     |
| ARM            | Cortex-A57      | #852523         | N/A                     |
| ARM            | Cortex-A57      | #832075         | ARM64_ERRATUM_832075    |
| ARM            | Cortex-A57      | #834220         | ARM64_ERRATUM_834220    |
| ARM            | Cortex-A57      | #1319537        | N/A                     |
| ARM            | Cortex-A72      | #1319367        | N/A                     |
| ARM            | Cortex-A72      | #853709         | N/A                     |
| ARM            | Cortex-A73      | #858921         | ARM_ERRATUM_858921      |
| ARM            | Cortex-A76      | #1165522        | N/A                     |
| ARM            | Cortex-A76      | #1286807        | ARM64_ERRATUM_1286807   |
| ARM            | Neoverse-N1     | #1165522        | N/A                     |
| ARM            | Neoverse-N1     | #1286807        | ARM64_ERRATUM_1286807   |
| ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412   |
| ARM            | MMU-500         | #842869         | N/A                     |
